MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 233

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see
Register2
Priorities"”).
4.31.4.2.1
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the value stored in the
comparator address/data registers. Further qualification of the type of access (R/W, word/byte) is possible.
Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact address is
compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n)
but does not cause a match.
considerations with data bus comparison. To compare byte accesses DBGADH must be loaded with the data byte and the low
byte must be masked out using the DBGADLM mask register. On word accesses the data byte of the lower address is mapped
to DBGADH.
Comparator A features an NDB control bit to determine if a match occurs when the data bus differs to comparator register
contents, or when the data bus is equivalent to the comparator register contents.
4.31.4.2.2
Comparator B features SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the
same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access
causes a match. Thus if configured for a byte access of a particular address, a word access covering the same address does not
lead to match.
Freescale Semiconductor
Table 309. Comparator A Data Bus Considerations
Table 310. Comparator Access Size Considerations
Note:
182.
(DBGC2)"”). Comparator channel priority rules are described in the priority section
Access
Word
Word
Word
Byte
Comparator B
Comparator B
Comparator B
Comparators
Comparator
A and C
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address
register must contain the exact address used in the code.
Exact Address Comparator Match (Comparators A and C)
Exact Address Comparator Match (Comparator B)
Address
ADDR[n]
ADDR[n]
ADDR[n]
ADDR[n]
Table 310
Address
ADDR[n]
ADDR[n]
ADDR[n]
ADDR[n]
DBGADH
Data[n]
Data[n]
Data[n]
x
lists access considerations without data bus compare.
DBGADL
Data[n+1]
Data[n+1]
SZE
x
x
—
0
1
1
SZ8
—
DBGADHM
X
0
1
$FF
$FF
$FF
$00
Word and byte accesses of ADDR[n]
Word and byte accesses of ADDR[n]
DBGADLM
Word accesses of ADDR[n]
$FF
$FF
$00
$00
Condition For Valid Match
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
Byte accesses of ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
MOVB #$BYTE ADDR[n]
S12S Debug (S12SDBGV1) Module
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
Section 4.31.3.2.4, “Debug Control
Example Valid Match
(Section 4.31.4.3.4, “Channel
Table 309
(182)
lists access
(182)
(182)
MM912F634
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