MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 94

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 112. PWM Prescale Clock Select Register (PWMPRCLK)
Note:
Functional Description and Application Information
4.13.3.1.4
The CAEx bits select either center aligned outputs or left aligned output for both PWM channels. If the CAEx bit is set to a one,
the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left
aligned. See
description of the PWM output modes.
4.13.3.2
This register selects the prescale clock source for clocks A and B independently.
Freescale Semiconductor
Offset
88.
Table 113. PWMPRCLK - Register Field Descriptions
Reset
W
R
PCKB[2:0]
PCKA[2:0]
(88)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
6–4
2–0
0x61
Section 4.13.4.2.5, “Left Aligned Outputs"”
PWM Prescale Clock Select Register (PWMPRCLK)
7
0
0
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channel 1. These three bits
determine the rate of clock B, as shown in
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channel 0. These three bits
determine the rate of clock A, as shown in
PWM Center Align Enable (CAEx)
Write these bits only when the corresponding channel is disabled.
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is
changed while a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition.
Table 114. Clock B Prescaler Selects
PCKB2
6
0
PCKB2
0
0
0
0
1
1
1
1
PCKB1
0
5
PCKB1
0
0
1
1
0
0
1
1
Table
Table
and
PCKB0
NOTE
NOTE
Section 4.13.4.2.6, “Center Aligned Outputs"”
114.
115.
0
4
PCKB0
0
1
0
1
0
1
0
1
Description
0
0
3
Value of Clock B
D2D clock / 128
D2D clock / 16
D2D clock / 32
D2D clock / 64
D2D clock / 2
D2D clock / 4
D2D clock / 8
D2D clock
PCKA2
0
2
PWM Control Module (PWM8B2C)
PCKA1
1
0
Access: User read/write
for a more detailed
MM912F634
PCKA0
0
0
94