MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 103

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.13.4.2.3
Dedicated period and duty registers exist for each channel and are double buffered, so if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.
If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer.
A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers,
and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition,
since the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used
to make adjustments
4.13.4.2.4
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see
“PWM Clock Select"”
period register as shown in
causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently
depending on what output mode is selected as shown in
and
Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of
both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the
channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM
counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the
channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next
selected clock.
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a
counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the
channel is disabled, except that the new period is started immediately with the output set according to the polarity bit.
The counter is cleared at the end of the effective period (see
“Center Aligned Outputs"”
Freescale Semiconductor
Section 4.13.4.2.6, “Center Aligned
•
•
•
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
PWM Period and Duty
When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur.
Depending on the polarity bit, the duty registers will contain the count of either the high time
or the low time.
PWM Timer Counters
To start a new “clean” PWM waveform without any “history” from the old waveform, writing
the channel counter (PWMCNTx) must happen prior to enabling the PWM channel
(PWMEx = 1).
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to
occur.
for the available clock sources and rates). The counter compares to two registers, a duty register and a
for more details).
Figure
26. When the PWM counter matches the duty register, the output flip-flop changes state,
Outputs"”.
Figure 26
NOTE
NOTE
Section 4.13.4.2.5, “Left Aligned Outputs"”
and described in
Section 4.13.4.2.5, “Left Aligned Outputs"”
PWM Control Module (PWM8B2C)
and
Section 4.13.4.2.6,
Section 4.13.4.1,
MM912F634
103