MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 211

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This
provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol.
It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device.
If desired, without the need for waiting for the ACK pulse.
The commands are described as follows:
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed, and the data is then ready for reading out
by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the
BKGD serial pin, and when the data bus cycle is complete. See
Section 4.30.4.4, “Standard BDM Firmware Commands"”
The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to
evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host
knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol
the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a
valid command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK
pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command
could be aborted using the SYNC command.
The GO_UNTIL
the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host
wants to trace if a breakpoint match occurs, and causes the CPU to enter active background mode. Note that the ACK is issued
whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The
ACK pulse related to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction
of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.
4.30.4.9
The SYNC command is unlike other BDM commands, because the host does not necessarily know the correct communication
speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC
command, the host should perform the following steps:
Freescale Semiconductor
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ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU
command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response.
ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the
appropriate places in the protocol.
Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest
serial communication frequency is determined by either DCO clock or external crystal oscillator depending on the
configuration chosen in the CRG.)
Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host
clock.)
Remove all drive to the BKGD pin so it reverts to high-impedance.
Listen to the BKGD pin for the sync response pulse.
(169)
SYNC — Request Timed Reference Pulse
command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when
for more information on the BDM commands.
Section 4.30.4.3, “BDM Hardware Commands"”
Background Debug Module (S12SBDMV1)
and
MM912F634
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