MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 206

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a
logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
The receive cases are more complicated.
asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived
start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target
clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles
after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
Freescale Semiconductor
Start of Bit Time
Start of Bit Time
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
Transmit 1
Transmit 0
BKGD Pin
BKGD Pin
Perceived
Perceived
Speedup
Drive to
Pulse
Host
Host
Host
Synchronization
Uncertainty
High-impedance
Figure 63. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 62. BDM Host-to-Target Serial Bit Timing
Figure 63
10 Cycles
R-C Rise
10 Cycles
10 Cycles
shows the host receiving a logic 1 from the target system. Since the host is
Target Senses Bit
Host Samples
High-impedance
BKGD Pin
Background Debug Module (S12SBDMV1)
High-impedance
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of
MM912F634
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