MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 237

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.5.3
In Normal mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows:
LBRA, BRA, BSR, BGND, as well as non-indexed JMP, JSR, and CALL instructions, are not classified as change of flow and are
not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate
whether the stored address was a source address or destination address.
MARK1
MARK2
SUB_1
ADDR1
IRQ_ISR
MARK1
IRQ_ISR
SUB_1
ADDR1
Freescale Semiconductor
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Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts, except for BDM vectors
LDX
JMP
NOP
BRN
NOP
DBNE
LDAB
STAB
RTI
LDX
JMP
LDAB
STAB
RTI
BRN
NOP
DBNE
Normal Mode
When a COF instruction with destination address is executed, the destination address is
stored to the trace buffer on instruction completion, indicating the COF has taken place. If
an interrupt occurs simultaneously, then the next instruction carried out is actually from the
interrupt service routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
In the following example, an IRQ interrupt occurs during execution of the indexed JMP at
address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ
service routine, but the destination address is entered into the trace buffer to indicate that
the indexed JMP COF has taken place.
The execution flow taking into account the IRQ is as follows
#SUB_1
0,X
*
A,PART5
#$F0
VAR_C1
#SUB_1
0,X
#$F0
VAR_C1
*
A,PART5
NOTE
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
;
;
;
;
;
S12S Debug (S12SDBGV1) Module
MM912F634
237