MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 283

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.36.3.4.8
The FRSV5 register is reserved for factory testing.
Table 382. Flash Reserved5 Register (FRSV5)
All FRSV5 bits read 0 and are not writable.
4.36.4
4.36.4.1
Flash command operations are used to execute program, erase, and erase verify algorithms described in this section. The
program and erase algorithms are controlled by the Flash memory controller whose time base, FCLK, is derived from the bus
clock via a programmable divider.
The next sections describe:
4.36.4.1.1
Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the bus clock down
to within the 150 to 200 kHz range.
If we define:
then FCLKDIV bits PRDIV8 and FDIV[5:0] are to be set as described in
For example, if the bus clock frequency is 20 MHz, FCLKDIV bits FDIV[5:0] should be set to 0x0C (001100), and bit PRDIV8 set
to 1. The resulting FCLK frequency is then 192 kHz. In this case, the Flash program and erase algorithm timings are increased
over the optimum target by:
Freescale Semiconductor
0x010F
Reset
W
R
1.
2.
3.
4.
•
•
How to write the FCLKDIV register to set FCLK
Command write sequences to program, erase, and erase verify operations on the Flash memory
Valid Flash commands
Effects resulting from illegal Flash command write sequences or aborting Flash operations
FCLK as the clock of the Flash timing control block
INT(x) as taking the integer part of x (e.g. INT(4.323) = 4)
Functional Description
Flash Command Operations
0
0
7
Flash Reserved5 Register (FRSV5)
Writing the FCLKDIV Register
The values loaded into the FCLKDIV register are different that those loaded into the
FCLKDIV register on prior S12 Flash modules, as they were based on the oscillator
frequency.
0
0
6
5
0
0
(200 - 192)/200 = 4%
NOTE
0
0
4
Figure
0
0
3
85.
32 kbyte Flash Module (S12SFTSR32KV1)
0
0
2
1
0
0
MM912F634
0
0
0
Eqn. 1
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