MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 219

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 264. DBGSR Field Descriptions (continued)
4.31.3.2.3
Table 266. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Table 267. DBGTCR Field Descriptions
Freescale Semiconductor
Address: 0x0022
TSOURCE
Reset
TRCMOD
SSF[2:0]
TALIGN
W
R
Field
Field
2–0
3–2
6
0
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is in currently. During a debug session
on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then
these bits retain their value to reflect the last state of the state sequencer before disarming. If a debug session is ended by an
internal event, then the state sequencer returns to state 0 and these bits are cleared to indicate that state0 was entered during
the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Table
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is
secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
Trace Mode Bits — See
flow information is stored. In Loop1 mode, change of flow information is stored but redundant entries into trace memory are
inhibited. In Detail mode, address and data for all memory and register accesses is stored. In Pure PC mode the program
counter value for each instruction executed is stored. See
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
0
0
7
Debug Trace Control Register (DBGTCR)
Table 268. TRCMOD Trace Mode Bit Encoding
265.
TRCMOD
00
Table 265. SSF[2:0] — State Sequence Flag Bit Encoding
TSOURCE
0
6
101,110,111
Section 4.31.4.5.2, “Trace Modes"
SSF[2:0]
000
001
010
100
011
5
0
0
0
0
4
Description
Description
Table
Description
for detailed Trace Mode descriptions. In Normal mode, change of
Normal
State0 (disarmed)
268.
Current State
Final State
Reserved
0
3
State1
State2
State3
TRCMOD
S12S Debug (S12SDBGV1) Module
0
2
1
0
0
MM912F634
TALIGN
0
0
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