MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 324

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.4.3
During a SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial
clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection
of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a
master SPI device, the slave select line can be used to indicate multiple-master bus contention.
4.38.4.3.1
Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity.
The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format.
The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the
phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having
different requirements.
4.38.4.3.2
The first edge on the SCK line is used to clock the first data bit of the slave into the master, and the first data bit of the master
into the slave. In some peripherals, the first bit of the slave’s data is available at the slave’s data out pin as soon as the slave is
selected. In this format, the first SCK edge is issued a half cycle after SS has become low.
A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched
from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit.
After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial
input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered
edges and shifted on even numbered edges.
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer, and is transferred to the
parallel SPI data register after the last bit is shifted in.
After the 16th (last) SCK edge:
Freescale Semiconductor
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Data that was previously in the master SPI data register should now be in the slave data register, and the data that was
in the slave data register should be in the master.
The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
Transmission Formats
Clock Phase and Polarity Controls
CPHA = 0 Transfer Format
SHIFT REGISTER
GENERATOR
BAUD RATE
MASTER SPI
Figure 102. Master/Slave Transfer Block Diagram
MISO
MOSI
SCK
SS
V
DD
MISO
MOSI
SCK
SS
Serial Peripheral Interface (S12SPIV4)
SHIFT REGISTER
SLAVE SPI
MM912F634
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