MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 242

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 318. Breakpoint Mapping Summary
Functional Description and Application Information
4.31.4.7.2
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the TALIGN bit. If a tracing
session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin
aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see
tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the DBG module is
disarmed.
4.31.4.7.3
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the
associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator
channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and
the breakpoint to SWI is suppressed.
4.31.4.7.3.1
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of
BDM firmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE
command, tagging into BDM is disabled. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests,
if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets
executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is
attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code, checks the ENABLE,
and returns if ENABLE is not set. If not serviced by the monitor, then the breakpoint is re-asserted when the BDM returns to
normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address, then an SWI in user code and DBG breakpoint
could occur simultaneously. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the
BDM/SWI service routine, care must be taken to avoid a repeated breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction
is the first instruction executed when normal program execution resumes.
Freescale Semiconductor
DBGBRK
0
1
X
1
1
Breakpoints Generated Via the TRIG Bit
Breakpoint Priorities
DBG Breakpoint Priorities and BDM Interfacing
When program control returns from a tagged breakpoint using an RTI or BDM GO command
without program counter modification, it will return to the instruction whose tag generated
the breakpoint. To avoid a repeated breakpoint at the same location, reconfigure the DBG
module in the SWI routine, if configured for an SWI breakpoint, or over the BDM interface,
by executing a TRACE command before the GO to increment the program flow past the
tagged instruction.
BDM Bit (DBGC1[4])
X
X
0
1
1
BDM Enabled
X
X
1
0
1
NOTE
BDM Active
X
X
0
1
0
S12S Debug (S12SDBGV1) Module
Breakpoint Mapping
Breakpoint to BDM
Breakpoint to SWI
Breakpoint to SWI
No Breakpoint
No Breakpoint
Table
317). If no
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