MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 193

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.29.4.4
The priority (from highest to lowest) and address of all exception vectors issued by the 9S12I32PIMV1 module upon request by
the CPU is shown in
Table 249. Exception Vector Map and Priority
4.29.5
4.29.5.1
After system reset, software should:
4.29.5.2
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests, per default. In order to make
an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, other
I bit maskable interrupt requests can interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
Freescale Semiconductor
Note:
171.
(Vector base + 0x00F0–0x0082)
2.
3.
1.
2.
3.
•
1.
2.
3.
4.
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0080)
16 bits vector address based
Vector Address
Clock monitor reset request
COP watchdog reset request
Initialize the interrupt vector base register if the interrupt vector table is not located at the default location
(0xFF80–0xFFF9).
Enable I bit maskable interrupts by clearing the I bit in the CCR.
Enable the X bit maskable interrupt by clearing the X bit in the CCR.
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
Service interrupt, e.g., clear interrupt flags, copy data, etc.
Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests)
Process data
Return from interrupt by executing the instruction RTI
0xFFFC
0xFFFE
0xFFFA
Initialization/Application Information
Exception Priority
Initialization
Interrupt Nesting
Table
(171)
249.
Pin reset, power-on reset, illegal address reset
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
X bit maskable interrupt request (D2DI error interrupt)
D2DI interrupt request
Device specific I bit maskable interrupt sources (priority determined by the low byte of the vector address,
in descending order)
Spurious interrupt
Source
Interrupt Module (S12SINTV1)
MM912F634
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