MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 97

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 119. PWM Channel Period Registers (PWMPERx)
Note:
Functional Description and Application Information
4.13.3.6
There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM
channel.
The period registers for each channel are double buffered, so if they change while the channel is enabled, the change will NOT
take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.
If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer.
See
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it
by the value in the period register for that channel:
For boundary case programming values, please refer to
Freescale Semiconductor
Offset
92.
Reset
W
R
•
•
•
•
•
•
Section 4.13.4.2.3, “PWM Period and Duty"”
(92)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
Left aligned output (CAEx = 0)
PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)
PWMx Period = Channel Clock Period * (2 * PWMPERx)
0x66/0x67
Bit 7
PWM Channel Period Registers (PWMPERx)
7
0
Reads of this register return the most recent value written. Reads do not necessarily return
the value of the currently active period due to the double buffering scheme.
6
0
6
0
5
5
for more information.
Section 4.13.4.2.7, “PWM Boundary
NOTE
0
4
4
0
3
3
0
2
2
PWM Control Module (PWM8B2C)
Cases"”.
1
0
1
Access: User read/write
MM912F634
Bit 0
0
0
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