MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 240

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.5.4.3
Table 316. PCH Field Descriptions
4.31.4.5.5
The data stored in the Trace Buffer can be read, provided the DBG module is not armed, is configured for tracing (TSOURCE bit
is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer
can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0
and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out first-in
first-out. By reading CNT in DBGCNT, the number of valid lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading, an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the
oldest data entry, thus if no overflow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace
buffer read sequence to be easily restarted from the oldest data entry.
The least significant word of line is read out first. This corresponds to the fields 1 and 0 of
field 2 in the least significant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed, will return invalid data and no shifting of the RAM pointer will occur.
4.31.4.5.6
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace
session information from immediately before the reset occurred, can be read out and the number of valid lines in the trace buffer
is indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking the trace buffer and
points to the oldest valid data, even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE
must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled
using end trigger alignment, since the reset may occur before the trace trigger, which in the begin trigger alignment case means
no information would be stored in the trace buffer.
The Trace Buffer contents and DBGCNT bits are undefined following a POR
Freescale Semiconductor
PC17
PC16
Field
CSD
CVA
3
2
1
0
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source
or destination address. This bit has no meaning in Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector
addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in
Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal, Pure PC, and Loop1 mode this bit corresponds to program counter bit 16.
Field2 Bits in Normal, Pure PC and Loop1 Modes
Reading Data from Trace Buffer
Trace Buffer Reset State
Table 315. Information Bits PCH
Bit 3
CSD
Bit 2
CVA
Description
PC17
Bit 1
PC16
Bit 0
Table
S12S Debug (S12SDBGV1) Module
312. The next word read returns
MM912F634
240