MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 163

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
The system clock can be supplied in several ways enabling a range of system operating frequencies to be supported:
The clock generated by the FLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in
Figure
The Flash memory is supplied by the bus clock which is also being used as a time base to derive the program and erase times
for the NVM.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator.
The clock monitor can be configured to generate a system reset if it is allowed to time out as a result of no oscillator clock being
present.
4.26.6
The MCU can operate in different chip modes. These are described in
The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These
are described in
Some modules feature a software programmable option to freeze the module status whilst the background debug module is
active to facilitate debugging. This is described in
4.26.6.1
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see
the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the
MODC signal is registered into this bit on the rising edge of RESET.
4.26.6.1.1
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires
the reset vector to be programmed correctly).The processor program is executed from internal memory.
4.26.6.1.2
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug
module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for
additional serial commands through the BKGD pin.
4.26.6.2
The MCU features two main low-power modes. Consult the respective module description for module specific behavior in system
stop and system wait mode. An important source of information about the clock system is the Clock and Reset Generator
description (CRG).
Freescale Semiconductor
•
•
45, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals.
The on-chip frequency locked loop (FLL).
The oscillator.
Modes of Operation
Chip Configuration Summary
Power Modes
4.26.6.2 Power
Normal Single-chip Mode
Special Single-chip Mode
Modes.
Table 214. Chip Modes
Normal single chip
Special single chip
Chip Modes
4.26.6.2.4 Freeze
Mode.
4.26.6.1 Chip Configuration
MODC
1
0
MM912F634 - MCU Die Overview
Table
Summary.
214). The MODC bit in
MM912F634
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