MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 205

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
“BDM Serial Interface"”
selected.
4.30.4.6
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which
selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
BDM.
The BDM serial interface is timed based on DCO clock or external reference clock depending on the configuration used (refer to
the CRG Block Guide for more details), which gets divided by five. This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate
the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data transfers the most
significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between the falling
edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level.
Since R-C rise time could be unacceptably long, the target system and host provide brief driven high (speedup) pulses to drive
BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases.
The timing for host-to-target is shown in
the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can
take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of
the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
earlier. Synchronization between the host and target is established in this manner at the start of every bit time.
Figure 62
is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target
recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD
Freescale Semiconductor
Hardware
Hardware
Firmware
Firmware
TRACE
Read
Write
Read
Write
GO,
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host
BDM Serial Interface
AT ~16 TC/Bit
Command
Command
Command
Command
Command
and
8 Bits
Section 4.30.3.2.1, “BDM Status Register (BDMSTS)"”
DELAY
48-BC
76-BC
Delay
AT ~16 TC/Bit
Figure 62
Address
Address
16 Bits
Data
Figure 61. BDM Command Structure
Command
Next
Data
and that of target-to-host in
DELAY
36-BC
150-BC
Delay
Command
Command
Next
Next
Data
Figure 63
AT ~16 TC/Bit
Background Debug Module (S12SBDMV1)
for information on how serial clock rate is
16 Bits
and
Data
BC = Bus Clock Cycles
TC = Target Clock Cycles
150-BC
Delay
Figure
64. All four cases begin when
Command
Command
Next
Next
MM912F634
205