MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 120

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.15.3.3
In this section, the receiver block diagram
data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver
wake-up function are explained.
The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in SCIC2. Character frames
consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode,
refer to
8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is
transferred to the receive data register and the receive data register full (RDRF) status flag is set. If RDRF was already set
indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because
the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data
buffer must be read to avoid a receiver overrun.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading
SCID. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s
program that handles receive data. Refer to
4.15.3.3.1
The SCI receiver uses a 16 baud rate clock for sampling. The receiver starts by taking logic level samples at 16 times the baud
rate to search for a falling edge on the RxD serial data input pin. A falling edge is defined as a logic 0 sample after three
consecutive logic 1 samples. The 16 baud rate clock is used to divide the bit time into 16 segments labeled RT1 through RT16.
When a falling edge is located, three more samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and
not merely noise. If at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character.
The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to determine the logic level for
that bit. The logic level is interpreted to be that of the majority of the samples taken during the bit time. In the case of the start bit,
the bit is assumed to be 0 if at least two of the samples at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at
RT8, RT9, and RT10 are 1s. If any sample in any bit time (including the start and stop bits) in a character frame fails to agree
with the logic level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive data buffer.
The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is
resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It
does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character
frame.
In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a
falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately.
In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared.
The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set.
4.15.3.3.2
Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended
for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they
determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2.
When RWU bit is set, the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is
set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the
end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up
in time to look at the first character(s) of the next message.
Freescale Semiconductor
Section •, “8- and 9-bit data
Receiver Functional Description
Data Sampling Technique
Receiver Wake-up Operation
modes".” For the remainder of this discussion, we assume the SCI is configured for normal
(Figure
Section 4.15.3.4, “Interrupts and Status
32) is used as a guide for the overall receiver functional description. Next, the
Serial Communication Interface (S08SCIV4)
Flags"” for more details about flag clearing.
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