MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 164

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.26.6.2.1
The system stop mode is entered if the CPU executes the STOP instruction. Asserting RESET, D2DINT, or any other interrupt
that is not masked exits system stop mode. System stop mode can be exited by CPU activity - depending on the configuration
of the interrupt request.
4.26.6.2.2
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal
CPU clock is switched off. All peripherals can be active in system wait mode. For further power reduction the peripherals can
individually turn off their local clocks. Asserting RESET, D2DINT, or any other interrupt that is not masked ends system wait mode.
4.26.6.2.3
Although this is not a low-power mode, unused peripheral modules should be disabled in order to save power.
4.26.6.2.4
The COP and RTI module provide a software programmable option to freeze the module status when the background debug
module is active. This is useful when debugging application software. For detailed description of the behavior of the COP and
RTI when the background debug module is active consult the corresponding module descriptions.
4.26.7
4.26.7.1
The MCU security feature allows the protection of the on chip Flash. For a detailed description of the security features refer to
the
4.26.8
Consult the S12SCPU manual and the
processing.
4.26.8.1
Resets are explained in detail in the
4.26.8.2
Table 215
(9S12I32PIMV1)“) provides an interrupt vector base register (IVBR) to relocate the vectors.
Freescale Semiconductor
Table 215. Interrupt Vector Locations
4.36.6, “Flash Module Security“
Vector Address
Vector base + $F8
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
lists all interrupt sources and vectors in the order of priority. The interrupt module
$FFFE
$FFFC
$FFFA
Security
Resets and Interrupts
MC9S12I32
Resets
Vectors
System Stop Mode
Wait Mode
Run Mode
Freeze Mode
(153)
description.
System reset or illegal access reset
4.27, “Port Integration Module (9S12I32PIMV1)“
Unimplemented instruction trap
4.27, “Port Integration Module (9S12I32PIMV1)“
D2DI External Error Interrupt
Oscillator monitor reset
COP watchdog reset
D2DI Error Interrupt
Interrupt Source
SWI
Mask
None
None
None
None
None
CCR
X Bit
I bit
description.
description for information on exception
(4.27, “Port Integration Module
MM912F634 - MCU Die Overview
D2DIE (D2DCTL1)
CRGCTL0 (CME)
COP rate select
Local Enable
None
None
None
None
MM912F634
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