MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 86

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 105. Low Side Status Register (LSSR)
Table 107. Low Side Enable Register (LSEN)
Note:
Note:
Functional Description and Application Information
4.12.3.2.2
4.12.3.2.3
Freescale Semiconductor
Offset
Offset
Table 104. LSCR - Register Field Descriptions (continued)
83.
Table 106. LSSR - Register Field Descriptions
85.
Note:
Reset
Reset
84.
3 - PWMLS2
2 - PWMLS1
W
W
R
R
7 - LSOTC
3 - LS2CL
2 - LS1CL
1 - LS2OL
0 - LS1OL
1 - LS2
0 - LS1
(83)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(85)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
When the Low Side is in OFF state, the Open Load Detection function is not operating. When reading the LSSR register while the Low
Side is operating in PWM and is in the OFF state, the LS1OL and LS2OL bits will not indicate Open Load.
0x31
0x32
LSOTC
7
0
7
0
0
PWM Enable for LS2
0 - PWM disabled on LS2
1 - PWM enabled on LS2 (Channel as selected with PWMCS2)
PWM Enable for LS1
0 - PWM disabled on LS1
1 - PWM enabled on LS1 (Channel as selected with PWMCS1)
LS2 Enable; LSEN has to be written once to control the LS2 Driver
LS1 Enable; LSEN has to be written once to control the LS1 Driver
Low Side Over-temperature condition present. Both drivers are turned off. Reading the register will clear the LSOT interrupt
flag if present. See
Low Side 2 Current Limitation
Low Side 1 Current Limitation
Low Side 2 Open Load
Low Side 1Open Load
Low Side Status Register (LSSR)
Low Side Control Enable Register (LSCEN)
6
0
0
6
0
0
Section 4.6, “Interrupts"
(84)
(84)
0
0
0
0
5
5
for details.
0
0
0
0
4
4
Description
Description
LS2CL
0
0
3
3
LS1CL
0
0
2
2
LSCEN
LS2OL
Low Side Drivers - LSx
1
0
1
0
Access: User read/write
Access: User read
MM912F634
LS1OL
0
0
0
0
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