MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 183

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM registers will also be
visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0xFF.
4.28.3.2.2
4.28.3.2.2.1
The program page index register in MMC allows accessing up to 256 kbyte of FLASH or ROM in the global memory map by using
the four page index bits to page 16x16 kbyte blocks into the program page window located from address 0x8000 to address
0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE register can be read or
written by normal memory accesses as well as by the CALL and RTC instructions (see
Instructions").
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64 kilobyte local CPU
address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE
register will be set to the appropriate value when the service routine is called. However an interrupt service routine can call other
routines that are in paged memory. The upper 16 kilobyte block of the local CPU memory space (0xC000–0xFFFF) is unpaged.
It is recommended that all reset and interrupt vectors point to locations in this area or to the other unmapped pages sections of
the local CPU memory map.
4.28.3.2.2.2
PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global address. These registers
can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
The four BDMPPR Program Page index bits allow access to the full 256 kbyte address map that can be accessed with 17 address
bits.
The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is
executing a firmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for
further details. (see
Freescale Semiconductor
Expansion of the Local Address Map
Expansion of the CPU Local Address Map
Expansion of the BDM Local Address Map
Figure
53).
Memory Mapping Control (S12SMMCV1)
Section 4.28.4.1, “CALL and RTC
MM912F634
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