MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 104

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 120. PWM Timer Counter Conditions
4.13.4.2.5
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits
in the PWMCTL register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and
a period register as shown in the block diagram in
changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register
resets the counter and the output flip-flop, as shown in
duty register to the associated registers, as described in
0 to the value in the period register – 1.
To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency
for the channel (A, B, SA, or SB), and divide it by the value in the period register for that channel.
As an example of a left aligned output, consider the following case:
Freescale Semiconductor
When PWMCNTx register written to any value When PWM channel is enabled (PWMEx = 1).
•
•
•
PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a % of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Clock Source = E, where E = 10 kHz (100 µs period)
PWMx Frequency = 10 kHz/4 = 2.5 kHz
PWMx Period = 400 µs
PWMx Duty Cycle = 3/4 *100% = 75%
Counter Clears ($00)
Effective period ends
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
Left Aligned Outputs
Changing the PWM output mode from left aligned to center aligned output (or vice versa)
while channels are operating can cause irregularities in the PWM output. It is recommended
to program the output mode before enabling the PWM channel.
PPOLx = 0
PPOLx = 1
Figure 27. PWM Left Aligned Output Waveform
Counts from last value in PWMCNTx.
PWMDTYx
Figure
Figure
Counter Counts
26. When the PWM counter matches the duty register the output flip-flop
Section 4.13.4.2.3, “PWM Period and
NOTE
26, as well as performing a load from the double buffer period and
Period = PWMPERx
When PWM channel is disabled (PWMEx = 0)
PWM Control Module (PWM8B2C)
Duty"”. The counter counts from
Counter Stops
MM912F634
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