MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 262

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
If the Frequency Divider Rate is set lower or equal to three the RTI interrupt service routine will access the RTICTL register with
in a timing window which is less or equal the synchronization delay. Hence the interrupt service routine which access the RTICTL
register to clear the RTIF bit is executed such frequently that the RTIRT bits are permanently locked. Therefore the following
sequence is recommended if RTIRT bits should be changed for a current selected Frequency Divider Rate of two or three:
If the actual Frequency Divider Rate of the RTI is set to a rate higher than three the write access to clear the interrupt flag (RTIF
bit) in the RTICTL register can be used to modify the RTIRT bits of the RTICTL register.
4.34.7.3
Applications which frequently access the RTICNT register should follow below recommendations.
If the RTICNT register is accessed with in a timing window which is less or equal the synchronization delay the following
sequence is recommended:
If the RTICNT register is accessed in a timing window which is higher than the synchronization delay, only the RTICNT register
needs to be written and wait until next time-out occurs.
Freescale Semiconductor
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- Access the RTICTL register to clear the RTI interrupt flag (RTIF bit) and disable the RTI interrupt (clear RTIE bit) by a
single write access.
- Execute a software loop in which the RTICTL register is written to modify the RTIRT bits until the new Frequency
Divider Rate is taken (read back value of RTIRT bits equals new value)
- Access RTICTL register to enable RTI interrupts again.
- Access the RTICTL register to clear the RTI interrupt flag (RTIF bit) and disable the RTI interrupt (clear RTIE bit) by a
single write access.
- Execute a software loop in which the RTICNT register is written to modify the rate until the new Frequency Divider Rate
is taken (read back value of RTICNT bits equals new value)
- Access RTICTL register to enable RTI interrupts again.
Modification of Modulus Down Counter rate (RTICNT register)
Real Time Interrupt (S12SRTIV1)
MM912F634
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