MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 232

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.2
The DBG contains three comparators, A, B, and C. Each comparator compares the system address bus with the address stored
in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH
and DBGADL, and allows masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see
address range, whereby either an access inside or outside the specified range generates a match condition. The comparator
configuration is controlled by the control register contents and the range control by the DBGC2 contents.
A match can initiate a transition to another state sequencer state (see
comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW,
SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW
bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allows the size of access (word or byte)
to be considered in the compare. Only comparator B features SZE and SZ.
The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator will
qualify a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction
reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored;
the comparator address register must be loaded with the exact opcode address.
If the TAG bit is clear (forced type match), a comparator match is generated when the selected address appears on the system
address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory,
which precedes the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match
of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register.
Thus for an opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not verified again on
subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data
value when a subsequent match occurs.
Freescale Semiconductor
TAGHITS
SECURE
CPU BUS
READ TRACE DATA (DBG READ DATA BUS)
Comparator Modes
COMPARATOR A
COMPARATOR C
COMPARATOR B
Figure
70) configures comparators to monitor the buses for an exact address or an
Figure 70. DBG Overview
MATCH1
MATCH0
MATCH2
Section 4.31.4.4, “State Sequence
CONTROL
MATCH
LOGIC
TAG &
TRANSITION
STATE
S12S Debug (S12SDBGV1) Module
BREAKPOINT REQUESTS
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
Control"”). The
STATE
TRACE
CONTROL
TRIGGER
MM912F634
232