MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 198

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.30.3.2.1
Table 251. Register Global Address 0x3_FF01
4.30.3.2.2
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
Freescale Semiconductor
Note:
172.
173.
0x3_FF08
0x3_FF09
0x3_FF0A
0x3_FF0B
Special Single-Chip Mode
Address
Global
All Other Modes
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased
UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0
(Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed.
and can only be read if not secure (see also bit description).
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM
— All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered
Reset
W
R
not apply in special single chip mode).
firmware lookup table upon exit from BDM active mode.
by the BDM hardware or standard firmware lookup table as part of BDM command execution.
BDMPPR
Reserved
Reserved
Reserved
Register
Name
BDM Status Register (BDMSTS)
BDM Status Register (BDMSTS)
When BDM is made active, the CPU stores the content of its CCR register in the BDMCCR
register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not
0xD0, which is the reset value of the CCR register in this CPU mode. Out of reset in all other
modes, the BDMCCR register is read zero.
W
W
W
W
R
R
R
R
ENBDM
0
(172)
BPAE
0
7
Bit 7
0
0
0
Figure 60. BDM Register Summary (continued)
BDMACT
1
0
6
6
0
0
0
0
0
0
0
5
5
0
0
0
0
NOTE
SDV
4
0
0
4
0
0
0
0
TRACE
Background Debug Module (S12SBDMV1)
BPP3
0
0
3
3
0
0
0
BPP2
0
0
0
2
2
0
0
0
UNSEC
0
BPP1
(173)
0
1
1
0
0
0
MM912F634
BPP0
Bit 0
0
0
0
0
0
0
0
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