MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 214

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31
4.31.1
The S12SDBGV1 module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of
application software. The S12SDBGV1 module is optimized for S12SCPU debugging.
Typically the S12SDBGV1 module is used in conjunction with the S12SBDM module, whereby the user configures the
S12SDBGV1 module for a debugging session over the BDM interface. Once configured the S12SDBGV1 module is armed and
the device leaves BDM returning control to the user program, which is then monitored by the S12SDBGV1 module. Alternatively,
the S12SDBGV1 module can be configured over a serial interface using SWI routines.
4.31.1.1
4.31.1.2
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition
to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered
immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word
reads. Tracing is disabled when the MCU system is secured.
4.31.1.3
Freescale Semiconductor
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COF — Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
BDM — Background Debug mode
S12SBDM — Background Debug module
WORD — 16 bit data entity
Data Line — 20 bit data entity
CPU — S12SCPU module
DBG — S12SDBG module
Tag — Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the
execution stage a tag hit occurs.
Three comparators (A, B, and C)
— Comparators A compares the full address bus and full 16-bit data bus
— Comparator A features a data bus mask register
— Comparators B and C compare the full address bus only
— Each comparator features selection of read or write access cycles
— Comparator B allows selection of byte or word access cycles
— Comparator matches can initiate state sequencer transitions
Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin  Address Addmax
— Outside address range match mode, Address Addminor Address  Addmax
Two types of matches
— Tagged — This matches just before a specific instruction begins execution
— Force — This is valid on the first instruction boundary after a match occurs
Two types of breakpoints
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
Trigger mode independent of comparators
— TRIG Immediate software trigger
S12S Debug (S12SDBGV1) Module
Introduction
Glossary Of Terms
Overview
Features
S12S Debug (S12SDBGV1) Module
MM912F634
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