MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 146

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 191. ADC Status Register (ASR)
Table 193. ADC Conversion Control Register (ACCR)
Note:
Functional Description and Application Information
4.19.4.2.2
Offset
134.
4.19.4.2.3
Note:
Freescale Semiconductor
Offset
135.
Table 190. ACR - Register Field Descriptions (continued)
Table 192. ACR - Register Field Descriptions
Reset
Reset
4 - ADCRST
W
R
6 - 2p5CLF
W
CCNT3…0
R
(134)
PS2…0
7 - SCF
(135)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
2-0
3-0
0x81
0x82 (0x82 and 0x83 for 8-Bit access)
CH15
15
0
SCF
7
0
Analog Digital Converter RESET
0 - Analog Digital Converter in Normal Operation
1 - Analog Digital Converter in Reset Mode, all ADC registers will reset to initial values. The bit has to be cleared to allow
ADC operation.
ADC Clock Prescaler Select (D2DCLK to ADCCLK divider)
000 - 10
001 - 8
010 - 6
011 - 4
100 - 2
101 - 1
110 - 1
111 - 1
Sequence Complete Flag. Reading the ADC Status Register (ASR) will clear the Flag.
ADC Reference Voltage Current Limitation Flag
Conversion Counter Status. The content of CCNT reflects the current channel in conversion and the conversion of CCNT-1
being complete. The conversion order is CH15, CH0, CH1,..., CH14.
ADC Status Register (ASR)
ADC Conversion Control Register (ACCR)
CH14
14
0
13
0
0
2p5CLF
6
0
CH12
12
0
CH11
11
0
0
0
5
CH10
10
0
CH9
0
9
0
0
4
CH8
0
8
Description
Description
CH7
0
7
CCNT3
1
3
CH6
0
6
CH5
5
0
CCNT2
1
2
CH4
Analog Digital Converter - ADC
0
4
CH3
0
3
CCNT1
1
1
Access: User read/write
Access: User read/write
CH2
0
2
MM912F634
CH1
1
0
CCNT0
0
1
CH0
0
0
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