MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 300

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.37
4.37.1
This section describes the functionality of the die-to-die (D2DIV1) initiator block especially designed for low cost connections
between a microcontroller die (Interface Initiator) and an analog die (Interface Target) located in the same package.
The D2DI block
4.37.1.1
The D2DI is the initiator for a data transfer to and from a target typically located on another die in the same package. It provides
a set of configuration registers and two memory mapped 256 Byte address windows. When writing to a window, a transaction is
initiated sending a write command, followed by an 8-bit address and the data byte or word to the target. When reading from a
window, a transaction is initiated sending a read command, followed by an 8-bit address to the target. The target then responds
with the data. The basic idea is that a peripheral located on another die, can be addressed like an on-chip peripheral, except for
a small transaction delay.
4.37.1.2
The main features of this block are
Freescale Semiconductor
•
•
•
•
•
realizes the initiator part of the D2D interface, including supervision and error interrupt generation
generates the clock for this interface
disables/enables the interrupt from the D2D interface
Software transparent, memory mapped access to peripherals on target die
— 256 Byte address window
— Supports blocking read or write as well as non-blocking write transactions
Scalable interface clock divide by 1, 2, 3 of bus clock
Die-to-Die Initiator (D2DIV1)
Introduction
Overview
Features
Read Data Bus
Write Data Bus
D2DERR_INT
Address Bus
D2DINTI
xfr_wait
Figure 93. Die-to-Die Initiator (D2DI) Block Diagram
D2DIF
Bus Clock
D2DCLKDIV
n=1 … 8
D2DIE
D2DCW
/n
Die-to-Die Initiator (D2DIV1)
D2DDAT[7:0]
D2DCLK
D2DINT
MM912F634
300