MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 166

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.27
4.27.1
The Port Integration Module (PIM) establishes the interface between the S12I32 peripheral modules SPI and the Die-To-Die
Interface module (D2DI) to the I/O pins of the MCU. Depending on the package option the D2DI related pins may or may not be
available externally; if used in a dual-die package this interface is internal.
All pins support general purpose I/O functionality if not in use by the peripheral module. The PIM controls the signal prioritization
and multiplexing on the shared pins and the pull-down functionality on specific pins.
4.27.2
The Port Integration Module includes these distinctive registers:
A standard port A pin has the following features:
A standard port C and D pin has the following features:
4.27.3
Table 216. Memory Map
Freescale Semiconductor
Reserved
Reserved
Register
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
DDRA
Name
PTC
PTD
PTA
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6-pin port A associated with the SPI module
2-pin port C used as D2DI clock output and D2DI interrupt input
8-pin port D used as 8 or 4-bit data I/O for the D2DI interface
GPIO function shared on all pins
Pull-down devices on PC1 and PD7-0 if used as D2DI inputs
Reduced drive capability on port A on per pin basis
Data registers for ports A, C, and D, when used as general-purpose I/O
Data direction registers for ports A, C, and D, when used as general-purpose I/O
Port input register on port A
Reduced drive register on port A
Input/output selection
5.0 V output drive
5.0 V digital input
Input/output selection
2.5 V output drive
2.5 V digital input
Port Integration Module (9S12I32PIMV1)
W
W
W
W
W
W
R
R
R
R
R
R
Introduction
Features
Memory Map
PTD7
Bit 7
0
0
0
0
0
PTD6
6
0
0
0
0
0
DDRA5
PTD5
PTA5
5
0
0
0
DDRA4
PTA4
PTD4
4
0
0
0
DDRA3
PTD3
PTA3
3
0
0
0
Port Integration Module (9S12I32PIMV1)
DDRA2
PTD2
PTA2
2
0
0
0
DDRA1
PTC1
PTD1
PTA1
1
0
0
MM912F634
DDRA0
PTC0
PTD0
PTA0
Bit 0
0
0
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