MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 134

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 166. Timer Control Register 1 (TCTL1)
Table 169. Timer Control Register 2 (TCTL2)
Note:
Note:
Functional Description and Application Information
4.18.3.3.8
Offset
122.
4.18.3.3.9
123.
These four pairs of control bits configure the input capture edge detector circuits.
Freescale Semiconductor
Table 167. TCTL1 - Register Field Descriptions
Table 170. TCTL2 - Register Field Descriptions
EDGnB,EDGnA Input Capture Edge Control
Reset
Reset
W
W
R
Offset 0xC9
R
(122)
7,5,3,1
6,4,2,0
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(123)
Field
Field
OMn
OLn
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0xC8
EDG3B
OM3
Table 168. Compare Result Output Action
7
0
7
0
Output Mode bit
Output Level bit
Timer Control Register 1 (TCTL1)
These four pairs of control bits are encoded to specify the output action to be taken as a
result of a successful Output Compare on “n” channel. When either OMn or OLn, the pin
associated with the corresponding channel becomes an output tied to its IOC. To enable
output action by the OMn and OLn bits on a timer port, the corresponding bit in OC3M should
be cleared.
Timer Control Register 2 (TCTL2)
OMn
0
0
1
1
EDG3A
OL3
6
0
6
0
OLn
0
1
0
1
EDG2B
OM2
0
0
5
5
EDG2A
OL2
NOTE
0
0
4
4
Timer disconnected from output pin logic
Description
Description
Clear OCn output line to zero
Set OCn output line to one
Toggle OCn output line
EDG1B
OM1
0
0
3
3
Action
Basic Timer Module - TIM (TIM16B4C)
EDG1A
OL1
0
0
2
2
EDG0B
OM0
1
0
1
0
Access: User read/write
Access: User read/write
MM912F634
EDG0A
OL0
0
0
0
0
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