MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 210

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Figure 67
the command is aborted, a new command could be issued by the host computer.
true timing scale
Figure 68
connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a
pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued
along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse.
Since this is not a probable situation, the protocol does not prevent this conflict from happening.
Freescale Semiconductor
(Target MCU)
Drives SYNC
To BKGD Pin
BKGD Pin
Target MCU
BDM Clock
BKGD Pin
BKGD Pin
Drives to
shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is
Host
READ_BYTE
This information is being provided so that the MCU integrator will be aware that such a
conflict could occur.
the READ_BYTE Command
READ_BYTE CMD is Aborted
Host
and Starts to Execute
by the SYNC Request
Figure 67. ACK Abort Procedure at the Command Level
Memory Address
Target
Host SYNC Request Pulse
Figure 68. ACK Pulse and SYNC Request Conflict
BDM Decode
(Out of Scale)
ACK Pulse
16 Cycles
Host and
Target Drive
to BKGD Pin
At Least 128 Cycles
NOTE
Electrical Conflict
High-impedance
READ_STATUS
Host
SYNC Response
From the Target
(Out of Scale)
Target
Figure 67
Background Debug Module (S12SBDMV1)
New BDM Command
does not represent the signals in a
New BDM Command
Host
Speedup Pulse
Target
MM912F634
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