MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 99

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.13.4
4.13.4.1
There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on
the D2D clock.
Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the D2D clock. Clock SA uses clock A as an
input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a
reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in
increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two
clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).
The block diagram in
4.13.4.1.1
The input clock to the PWM prescaler is the D2D clock. The input clock can also be disabled when both PWM channels are
disabled (PWME1-0 = 0). This is useful for reducing power by disabling the prescale counter.
Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has
options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the D2D clock. The value selected for clock A is determined by the
PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1,
PCKB0 bits also in the PWMPRCLK register.
4.13.4.1.2
The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2.
The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2.
The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by
2. Similar rates are available for clock SB.
Freescale Semiconductor
Functional Description
PWM Clock Select
Prescale
Clock Scale
Figure 25
shows the four different clocks and how the scaled clocks are created.
PWM Control Module (PWM8B2C)
MM912F634
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