MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 238

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.5.3.1
Loop1 mode, similarly to Normal mode also stores only COF address information to the trace buffer, it however allows the filtering
out of redundant information.
The intent of Loop1 mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping
construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after
address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents
consecutive duplicate address entries in the Trace Buffer resulting from repeated branches.
Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping
constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these
would most likely indicate a bug in the user’s code that the DBG module is designed to help find.
LOOP
LOOP2
4.31.4.5.3.2
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to
supply additional information on indexed, indirect addressing modes, where storing only the destination address would not
provide all information required for a user to determine where the code is in error. This mode also features information bit storage
to the trace buffer, for each address byte storage. The information bits indicates the size of access (word or byte) and the type
of access (read or write).
When tracing in Detail mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle.
4.31.4.5.3.3
In Pure PC mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal opcodes are stored.
Freescale Semiconductor
INX
BRCLR
BRN
NOP
DBNE
Loop1 Mode
In certain very tight loops, the source address will have already been fetched again before
the background comparator is updated. This results in the source address being stored twice
before further duplicate entries are suppressed. This condition occurs with branch-on-bit
instructions when the branch is fetched by the first P-cycle of the branch or with
loop-construct instructions in which the branch is fetched with the first or second P cycle.
See examples below:
Detail Mode
Pure PC Mode
When tracing is terminated using forced breakpoints, latency in breakpoint generation
means that opcodes following the opcode causing the breakpoint can be stored to the trace
buffer. The number of opcodes is dependent on program flow. This should be avoided by
using tagged breakpoints.
*
CMPTMP,#$0c,LOOP
A,LOOP2
NOTE:
NOTE
; 1-byte instruction fetched by 1st P-cycle of BRCLR
; the BRCLR instruction also will be fetched by 1st
; P-cycle of BRCLR
; 2-byte instruction fetched by 1st P-cycle of DBNE
; 1-byte instruction fetched by 2nd P-cycle of DBNE
; this instruction also fetched by 2nd P-cycle of DBNE
S12S Debug (S12SDBGV1) Module
MM912F634
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