MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 118

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 138. SCI Data Register (SCID)
Note:
Functional Description and Application Information
4.15.2.7
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to
the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms
for the SCI status flags.
Offset
105.
4.15.3
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other
MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate
independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the
SCI, writes the data to be transmitted, and processes received data. The following describes each of the blocks of the SCI.
4.15.3.1
As shown in
SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to
use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to
the leading edge of the start bit and how bit sampling is performed.
The MCU resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in
the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. For a
Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5
percent for 8-bit data format and about ±4.0 percent for 9-bit data format. Although baud rate modulo divider settings do not
always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is
acceptable for reliable communications.
Freescale Semiconductor
Reset
W
R
(105)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0x47
Figure
Functional Description
R7
T7
SCI Data Register (SCID)
Baud Rate Generation
7
0
33, the clock source for the SCI baud rate generator is the D2D clock.
D2D
R6
T6
BAUD RATE GENERATOR
6
0
OFF IF [SBR12:SBR0] = 0
MODULO DIVIDE BY
(1 THROUGH 8191)
SBR12:SBR0
Figure 33. SCI Baud Rate Generation
R5
T5
0
5
R4
T4
0
BAUD RATE =
4
DIVIDE BY
Rx SAMPLING CLOCK
(16  BAUD RATE)
16
[SBR12:SBR0]  16
R3
T3
0
3
BUSCLK
Serial Communication Interface (S08SCIV4)
Tx BAUD RATE
R2
T2
0
2
R1
T1
1
0
Access: User read/write
MM912F634
R0
T0
0
0
118