MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 50

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Freescale Semiconductor
Table 65. Analog die Registers
0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)
Offset
0x9C
0x9D
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0x97
0x98
0x99
0x9A
0x9B
0x9E
0x9F
0xA2
0xA3
0xA4
0xA5
Timer System Control Reg 1
ADC Data Result Register 8
ADC Data Result Register 9
ADC Data Result Register 9
TIM InCap/OutComp Select
Timer Toggle Overflow Reg
Timer Compare Force Reg
Output Comp 3 Mask Reg
Output Comp 3 Data Reg
ADC Data Result Reg 10
ADC Data Result Reg 10
ADC Data Result Reg 11
ADC Data Result Reg 11
ADC Data Result Reg 12
ADC Data Result Reg 12
ADC Data Result Reg 14
ADC Data Result Reg 14
ADC Data Result Reg 15
ADC Data Result Reg 15
Timer Count Register
Timer Count Register
ADR10 (hi)
ADR10 (lo)
ADR12 (hi)
ADR12 (lo)
ADR14 (hi)
ADR14 (lo)
ADR15 (hi)
ADR15 (lo)
ADR11 (hi)
ADR11 (lo)
ADR8 (lo)
ADR9 (hi)
ADR9 (lo)
TCNT (hi)
TCNT (lo)
CFORC
TSCR1
OC3M
Name
OC3D
TTOV
TIOS
(60)
- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
adr10 9
adr10 1
adr12 9
adr12 1
adr14 9
adr14 1
adr15 9
adr15 1
adr11 9
adr11 1
tcnt 15
adr8 1
adr9 9
adr9 1
tcnt 7
TEN
7
0
0
0
0
0
adr10 8
adr10 0
adr12 8
adr12 0
adr14 8
adr14 0
adr15 8
adr15 0
adr11 8
adr11 0
tcnt 14
adr8 0
adr9 8
adr9 0
tcnt 6
6
0
0
0
0
0
0
adr10 7
adr12 7
adr14 7
adr15 7
adr11 7
tcnt 13
adr9 7
tcnt 5
5
0
0
0
0
0
0
0
0
0
0
0
0
0
adr10 6
adr12 6
adr14 6
adr15 6
adr11 6
TFFCA
tcnt 12
adr9 6
tcnt 4
4
0
0
0
0
0
0
0
0
0
0
0
0
adr10 5
adr12 5
adr14 5
adr15 5
OC3M3
OC3D3
adr11 5
tcnt 11
adr9 5
FOC3
tcnt 3
TOV3
IOS3
3
0
0
0
0
0
0
0
0
0
adr10 4
adr12 4
adr14 4
adr15 4
OC3M2
OC3D2
adr11 4
tcnt 10
adr9 4
FOC2
TOV2
tcnt 2
IOS2
2
0
0
0
0
0
0
0
0
0
adr10 3
adr11 3
adr12 3
adr14 3
adr15 3
OC3M1
OC3D1
adr9 3
FOC1
TOV1
tcnt 9
tcnt 1
IOS1
1
0
0
0
0
0
0
0
0
0
Introduction
MM912F634
adr10 2
adr11 2
adr12 2
adr14 2
adr15 2
OC3M0
OC3D0
adr9 2
FOC0
TOV0
tcnt 8
tcnt 0
IOS0
0
0
0
0
0
0
0
0
0
0
50