MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 113

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 128. SCI Control Register 1 (SCIC1)
Note:
Functional Description and Application Information
4.15.2.2
This read/write register is used to control various optional features of the SCI system.
Table 129. SCIC1 Field Descriptions
Freescale Semiconductor
Offset
98.
Reset
W
R
LOOPS
RSRC
Field
ILT
PE
PT
(98)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
M
7
5
4
2
1
0
0x42
LOOPS
Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the
transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD
Receiver Source Select — This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver
input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter
output.
0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (LSB first) + stop.
1 Receiver and transmitter use 9-bit data characters
Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count
toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Wake-up"” for more information.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of
the data character (eighth or ninth data bit) is treated as the parity bit.
0 No hardware parity generation or checking.
1 Parity enabled.
Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s
in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including
the parity bit, is even.
0 Even parity.
1 Odd parity.
SCI Control Register 1 (SCIC1)
7
0
pin is not used by SCI.
start + 8 data bits (LSB first) + 9th data bit + stop.
6
0
0
RSRC
0
5
M
0
4
Description
0
0
3
Serial Communication Interface (S08SCIV4)
ILT
0
2
Section 4.15.3.3.2.1, “Idle-line
PE
1
0
Access: User read/write
MM912F634
PT
0
0
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