MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 223

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 280. State1 Sequencer Next State Selection
The priorities described in
(0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches.
4.31.3.2.7.2
Table 281. Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in
State2. The matches refer to the match channels of the comparator match control logic as depicted in
in
comparator enable bit in the associated DBGXCTL control register.
Table 282. DBGSCR2 Field Descriptions
Table 283. State2 —Sequencer Next State Selection
The priorities described in
(0,1,2) has priority. The SC[2:0] encoding ensures that a match leading to final state has priority over all other matches
Freescale Semiconductor
Address: 0x0027
Reset
Section 4.31.3.2.8.1, “Debug Comparator Control Register
SC[2:0]
SC[2:0]
W
R
000
001
010
011
100
101
110
111
Field
2–0
SC[2:0]
000
001
010
100
101
011
110
111
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
Table 311
Table 311
0
0
6
dictate that in the case of simultaneous matches, the match on the lower channel number
dictate that in the case of simultaneous matches, the match on the lower channel number
Match2 has no affect, all other matches (M0,M1) to Final State
5
0
0
Either Match0 or Match1 to State2........... Match2 has no effect
Match2 to State1..... Match0 to Final State
Match1 to State3....... Match0 Final State
Match0 to State1....... Match2 to State3.
Match1 to State1........ Match2 to State3
Match1 to State3....... Match0 Final State
Match0 to State2....... Match1 to State3
Match0 to State2....... Match2 to State3
0
0
4
Match2 Final State
(DBGXCTL)"”. Comparators must be enabled by setting the
Match1 to State3
Match2 to State3
Any match to Final State
Description
Description
Match2 to State2
Match1 to State2
Match1 to State3
Description
0
0
3
SC2
S12S Debug (S12SDBGV1) Module
0
2
Figure 69
SC1
1
0
and described
MM912F634
SC0
0
0
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