MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 90

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.13
4.13.1
To control the High Side (HS1, HS2) and the Low Side (LS1, LS2) duty cycle as well as the PTB2 output, the PWM module is
implemented. Refer to the individual driver section for details on the use of the internal PWM1 and PWM0 signal
“High Side Drivers -
The PWM definition is based on the HC12 PWM definitions with some of the simplifications incorporated. The PWM module has
two channels with independent controls of left and center aligned outputs on each channel.
Each of the two channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select
scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent
continuous waveforms with software-selectable duty rates from 0% to 100%.
4.13.1.1
The PWM block includes these distinctive features:
4.13.1.2
The PWM8B2C module does operate in Normal mode only.
Freescale Semiconductor
•
•
•
•
•
•
•
•
Two independent PWM channels with programmable periods and duty cycles
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM
counter reaches zero), or when the channel is disabled
Programmable center or left aligned outputs on individual channels
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
Programmable clock select logic
PWM Control Module (PWM8B2C)
Introduction
Features
Modes of Operation
HS",
Section 4.12, “Low Side Drivers - LSx"
and
Section 4.17, “General Purpose I/O -
PWM Control Module (PWM8B2C)
PTB[0…2]")
(Section 4.11,
MM912F634
90