MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 213

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Background Debug Module (S12SBDMV1)
4.30.4.11
Serial Communication Timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more
than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting
for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep
waiting forever without any timeout limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission,
and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. However, if a new
falling edge is not detected by the target within 512 clock cycles since the last falling edge, a timeout occurs and the current
command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft reset will occur causing the
command to be disregarded. The data is not available for retrieval after the timeout has occurred. This is the expected behavior
if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch
(between BDM and CPU) when the hardware handshake protocol is enabled, the timeout between a read command and the data
retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from
an issued read command. However, once the handshake pulse (ACK pulse) is issued, the timeout feature is re-activated,
meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock
cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no
longer available for retrieval. Any negative edge in the BKGD pin after the timeout period is considered to be a new command or
a SYNC request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the timeout in the serial communication
is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative
edges, and the command being issued or data being retrieved is not complete, a soft reset will occur causing the partially received
command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft reset has occurred, is
considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
MM912F634
Freescale Semiconductor
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