MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 179

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Global map) within the 64 kByte Local map. The PPAGE index register is effectively used to construct paged Flash addresses in
the Local map format. The CPU has special access to read and write this register directly, during execution of CALL and RTC
instructions.
Table 241. PPAGE Field Descriptions
The fixed 16 k page from 0x0000 to 0x3FFF is the page number 0xFC. Parts of this page are covered by Register and RAM
space. See SoC Guide for details.
The fixed 16 k page from 0x4000–0x7FFF is the page number 0xFD.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x0000 and 0xFFFF out of reset.
The fixed 16 k page from 0xC000-0xFFFF is the page number 0xFF.
4.28.2.2.2
Table 242. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local
mapping scheme.
Freescale Semiconductor
Address: 0x0031
Reset
PIX[3:0]
W
R
Field
3–0
DP15
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 FLASH or ROM array pages is
to be accessed in the Program Page Window.
0
7
Direct Page Register (DIRECT)
Bit17
DP14
PPAGE Register [3:0]
0
6
Figure 49. PPAGE Address Mapping
DP13
5
0
Global Address [17:0]
Bit14
DP12
0
4
Bit13
Description
Address: CPU Local Address
DP11
0
3
Address [13:0]
or BDM Local Address
Memory Mapping Control (S12SMMCV1)
DP10
0
2
Bit0
DP9
1
0
MM912F634
DP8
0
0
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