MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 316

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.3.2.2
Table 404. SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
Table 405. SPICR2 Field Descriptions
Freescale Semiconductor
0x00E9
Reset
MODFEN
BIDIROE
SPISWAI
W
R
SPC0
Field
4
3
1
0
Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is
cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value
of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration, refer to
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state.
0 SS port pin is not used by the SPI.
1 SS port pin with MODF feature.
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer of the SPI,
when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, and
in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a
transmission in progress and force the SPI into idle state.
0 Output buffer disabled.
1 Output buffer enabled.
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode.
1 Stop SPI clock generation when in wait mode.
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
of this bit will abort a transmission in progress and force the SPI system into idle state.
0
0
7
Table 403. SS Input / Output Selection
SPI Control Register 2 (SPICR2)
MODFEN
0
0
1
1
0
0
6
SSOE
0
1
0
1
5
0
0
SS input with MODF feature
SS is slave select output
SS not used by the SPI
SS not used by the SPI
MODFEN
0
4
Master Mode
Description
BIDIROE
0
3
Serial Peripheral Interface (S12SPIV4)
0
0
2
Slave Mode
Table
SS input
SS input
SS input
SS input
406. In master mode, a change
SPISWAI
1
0
Table
406. In master
MM912F634
SPC0
0
0
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