MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 135

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 172. Timer Interrupt Enable Register (TIE)
Table 174. Timer System Control Register 2 (TSCR2)
Note:
Note:
Functional Description and Application Information
4.18.3.3.10
Offset
124.
4.18.3.3.11
Offset
125.
Freescale Semiconductor
Table 173. TIE - Register Field Descriptions
Table 175. TIE - Register Field Descriptions
Reset
Reset
W
W
R
R
(124)
(125)
C[3-0]I
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
TOI
3-0
7
0xCA
0xCB
TOI
7
0
0
7
0
Input Capture/Output Compare Interrupt Enable.
1 = Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt
0 = Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt
Timer Overflow Interrupt Enable
1 = Hardware interrupt requested when TOF flag set in TFLG2 register.
0 = Hardware Interrupt request inhibited.
Table 171. Edge Detector Circuit Configuration
Timer Interrupt Enable Register (TIE)
Timer System Control Register 2 (TSCR2)
This mode of operation is similar to an up-counting modulus counter.
If register TC3 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000
continuously. If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer
counter register (TCNT) is reset from $FFFF to $0000.
The newly selected prescale factor will not take effect until the next synchronized edge,
where all prescale counter stages equal zero.
EDGnB
0
0
1
1
6
0
0
6
0
0
EDGnA
0
1
0
1
0
0
0
0
5
5
NOTE
0
0
0
0
4
4
Capture on any edge (rising or falling)
Description
Description
Capture on falling edges only
Capture on rising edges only
TCRE
Capture disabled
Configuration
C3I
0
0
3
3
Basic Timer Module - TIM (TIM16B4C)
PR2
C2I
0
0
2
2
PR1
C1I
1
0
1
0
Access: User read/write
Access: User read/write
MM912F634
PR0
C0I
0
0
0
0
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