MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 207

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Figure 64
clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host
initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for
13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock
cycles after starting the bit time.
4.30.4.7
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be
modified relative to the bus clock, when modifying DCO clock or the bus clock divider, it is very helpful to provide a handshake
protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait
the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This
sub-section will describe the hardware handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the
target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This
pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see
This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued
command was a read command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL
command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures
enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command
and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow
due to long accesses taking place.This protocol allows a great flexibility for the POD designers, since it does not rely on any
accurate time measurement or short response time to any event in the serial communication.
Freescale Semiconductor
Start of Bit Time
Speedup Pulse
Target System
(Target MCU)
BDM Clock
BKGD Pin
BKGD Pin
Perceived
Drive and
Drive to
shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one
Host
Serial Interface Hardware Handshake Protocol
If the ACK pulse was issued by the target, the host assumes the previous command was
executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK
pulse will not be issued meaning that the BDM command was not executed. After entering
wait or stop mode, the BDM command is no longer pending.
Figure 64. BDM Target-to-Host Serial Bit Timing (Logic 0)
(169)
or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM
10 Cycles
10 Cycles
NOTE
High-impedance
Host Samples
BKGD Pin
Background Debug Module (S12SBDMV1)
Speedup Pulse
Next Bit
Earliest
Start of
MM912F634
Figure
65).
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