MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 147

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 195. ADC Conversion Complete Status Register (ACCSR)
Table 197. ADC Data Result Register x (ADRx)
Functional Description and Application Information
4.19.4.2.4
Note:
4.19.4.2.5
Note:
Freescale Semiconductor
Offset
136.
Offset
137.
Table 194. ACCR - Register Field Descriptions
Table 196. ACCSR - Register Field Descriptions
Table 198. ADRx - Register Field Descriptions
Reset
Reset
W
W
R
R
15-0 CCx
(136)
(137)
Field
ADRx
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
15-0
15-6
CHx
0x84 (0x84 and 0x85 for 8-Bit access)
0x86+x (0x86 and 0x87 for 8-Bit access)
CC15
15
15
0
0
Channel Select - If 1, the selected channel is included into the sequence. Writing ACCR will stop the current sequence and
restart. Writing ACCR=0 will stop the conversion, All CCx flags will be cleared when ACCR is written.Conversion will start
after write. 16-Bit write operation recommended, writing 8-bit: Only writing the High Byte will start the conversion with
Channel 15, if selected. Write to the Low Byte will not start a conversion.
Measure individual Channels by writing a sequence of one channel. Channel 15 needs to be selected in order to have the
offset compensation functional.
ADC - Channel X left adjusted Result Register. Reading the register will clear the corresponding CCx register in the ACCSR
register. 16-bit read recommended. 8-Bit read: Reading the low byte will latch the high byte for the next read, reading the
high byte will clear the cc flag.
Conversion Complete Flag - Indicates the conversion being complete for channel x. Read operation only.16-bit read
recommended. 8-Bit read will return the current status, no latching will be performed.
ADC Conversion Complete Status Register (ACCSR)
ADC Data Result Register x (ADRx)
CC14
14
14
0
0
13
13
0
0
0
CC12
12
12
0
0
CC11
11
11
0
0
ADRx
CC10
10
10
0
0
CC9
0
0
9
9
CC8
0
0
8
8
Description
Description
Description
CC7
0
0
7
7
CC6
0
0
6
6
CC5
5
0
5
0
0
CC4
Analog Digital Converter - ADC
0
0
0
4
4
CC3
0
0
0
3
3
CC2
0
0
0
2
2
Access: User read
Access: User read
MM912F634
CC1
1
0
1
0
0
CC0
0
0
0
0
0
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