MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 305

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 392. D2DI Status Register 0 (D2DSTAT0)
Table 394. D2DI Status Register 1 (D2DSTAT1)
Functional Description and Application Information
Table 391. D2DCTL1 Register Field Descriptions (continued)
4.37.3.2.3
This register reflects the status of the D2DI transactions.
Table 393. D2DI Status Register 0 Field Descriptions
4.37.3.2.4
This register holds the status of the external interrupt pin and an indicator about the D2DI transaction status.
Freescale Semiconductor
ACKERF
TIMOUT
Reset
0x00DA
0x00DB
CNCLF
TERRF
ERRIF
TIMEF
PARF
PAR1
PAR0
Field
Field
W
R
3:0
7
6
5
4
3
2
1
0
Time-out Setting — Defines the number of D2DCLK cycles to wait after the last transaction cycle until a timeout is asserted. In
case of a timeout the TIMEF flag in the D2DSTAT0 register will be set.
These bits are write once in normal modes and can always be written in special modes.
0000 The acknowledge is expected directly after the last transfer, i.e. the target must not insert a wait cycle.
0001 - 1111: The target may insert up to TIMOUT wait states before acknowledging a transaction until a timeout is asserted
D2DI error interrupt flag — This status bit indicates that the D2D initiator has detected an error condition (summary of the
following five flags).This interrupt is not locally maskable. Write a 1 to clear the flag. Writing a 0 has no effect.
0 D2DI has not detected an error during a transaction.
1 D2DI has detected an error during a transaction.
Acknowledge Error Flag— This read-only flag indicates that in the acknowledge cycle not all data inputs are sampled high,
indicating a potential broken wire. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
CNCLF — This read-only flag indicates the initiator has canceled a transaction and replaced it by an IDLE command due to a
pending error flag (ERRIF). This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
Time Out Error Flag — This read-only flag indicates the initiator has detected a timeout error. This flag is cleared when the ERRIF
bit is cleared by writing a 1 to the ERRIF bit.
Transaction Error Flag — This read-only flag indicates the initiator has detected the error signal during the acknowledge cycle of
the transaction. This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
Parity Error Flag — This read-only flag indicates the initiator has detected a parity error. Parity bits[1:0] contain further information.
This flag is cleared when the ERRIF bit is cleared by writing a 1 to the ERRIF bit.
Parity Bit — P[1] as received by the D2DI
Parity Bit — P[0] as received by the D2DI
ERRIF
7
0
7
D2DI Status Register 0 (D2DSTAT0)
D2DI Status Register 1 (D2DSTAT1)
ACKERF
6
0
6
CNCLF
0
5
5
TIMEF
0
4
4
Description
Description
TERRF
0
3
3
PARF
0
2
2
Die-to-Die Initiator (D2DIV1)
PAR1
1
0
1
Access: User read/write
Access: User read
MM912F634
PAR0
0
0
0
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