MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 217

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 259. Quick Reference to DBG Registers (continued)
4.31.3.2
This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of
registers that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When
ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
4.31.3.2.1
Table 260. Debug Control Register (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
Table 261. DBGC1 Field Descriptions
Freescale Semiconductor
Note:
Address: 0x0020
177.
178.
179.
180.
Address
0x002D
0x002E
0x002F
Reset
W
R
Field
ARM
7
This bit is visible at DBGCNT[7] and DBGSR[7]
This represents the contents if the Comparator A control register is blended into this address.
This represents the contents if the Comparator B control register is blended into this address.
This represents the contents if the Comparator C control register is blended into this address.
DBGADHM
DBGADLM
DBGADL
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is
automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting
this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
ARM
Name
Register Descriptions
0
7
Debug Control Register 1 (DBGC1)
When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not
affected by the write, since up until the write operation, ARM = 1 preventing these bits from
being written. These bits must be cleared using a second write if required.
W
W
W
R
R
R
TRIG
0
0
6
Bit 15
Bit 7
Bit 7
Bit 7
14
5
0
0
6
6
6
13
5
5
5
BDM
NOTE
0
4
Description
12
4
4
4
DBGBRK
0
3
11
3
3
3
S12S Debug (S12SDBGV1) Module
0
0
2
10
2
2
2
1
0
1
1
9
1
COMRV
MM912F634
Bit 0
Bit 0
Bit 8
Bit 0
0
0
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