MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 331

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.38.4.7.4
The reset values of registers and signals are described in
registers and their bit fields.
4.38.4.7.5
The S12SPIV4 only originates interrupt requests when the SPI is enabled (SPE bit in SPICR1 set). The following is a description
of how the S12SPIV4 makes a request, and how the MCU should acknowledge that request. The interrupt vector offset and
interrupt priority are chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
4.38.4.7.5.1
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see
Table
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will
stay active while the MODF flag is set. MODF has an automatic clearing process which is described in
Status Register
4.38.4.7.5.2
SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is
serviced. SPIF has an automatic clearing process, which is described in
4.38.4.7.5.3
SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced.
SPTEF has an automatic clearing process, which is described in
Freescale Semiconductor
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403). After MODF is set, the current transfer is aborted and the following bit is changed:
If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last
received from the master before the reset.
Reading from the SPIDR after reset will always read a byte of zeros.
MSTR = 0, The master bit in SPICR1 resets.
(SPISR)".
Reset
Interrupts
MODF
SPIF
SPTEF
Section 4.28.2, “Memory Map and
Section 4.38.3.2.4, “SPI Status Register
Section 4.38.3.2.4, “SPI Status Register
Serial Peripheral Interface (S12SPIV4)
Registers", which details the
Section 4.38.3.2.4, “SPI
(SPISR)".
(SPISR)".
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