MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 258

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.34
4.34.1
This section describes the functionality of the Real Time Interrupt module (RTI), a sub-block of the HCS12S core platform. The
RTI (free running real time interrupt) enables the user to generate a hardware interrupt at a fixed periodic rate. If RTI is enabled,
the interrupt will occur at the rate selected by the RTICTL and RTICNT register.
The RTI counter is clocked by the internal reference clock. At the end of the RTI timeout period the RTIF flag is set to one and a
new RTI timeout period starts immediately.
The RTI contains two asynchronous clock domains (one for the Modulus Down Counter/Prescaler and one for the register bank).
Information exchange between both clock domains is fully synchronized. Therefore modification of the RTI timeout period must
be done in appliance to the write protection rules.
4.34.2
A block diagram of the RTI is shown in
4.34.3
The RTI includes these distinctive features:
4.34.4
4.34.5
There are no external signals associated with this module.
Freescale Semiconductor
Int_Ref_Clock
bus clock
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Generate hardware interrupt at a fixed periodic rate
Software selectable RTI operation in WAIT and STOP mode
Software selectable RTI freeze during BDM active mode
Run Mode
If RTI functionality is required, the individual bits (RTIRT) of the associated rate select registers (RTICTL) have to be set
to a non-zero value. In addition, to generate RTI requests, the RTI must be enabled (RTIE bit set). The RTI counter is
stopped if all rate select bits in the RTICTL register are zero. Interrupt requests will be disabled if the corresponding bit
(RTIE) is cleared.
Wait mode
If the respective enable bit (RTISWAI) is cleared, the RTI will continue to run, else RTI will remain frozen.
Stop mode
If the respective enable bit (RTIRSTP) is set, the RTI will continue to run, else RTI will remain frozen.
Real Time Interrupt (S12SRTIV1)
Introduction
Overview
Features
Modes of Operation
External Signal Description
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RTIRT[1:0]
Prescaler
(1, 16, 256)
Figure 81
Modulus Down Counter
Figure 81. Block Diagram
RTICNT-Register
(1,...., 256)
RTIE
RTIF
Real Time Interrupt (S12SRTIV1)
RTI request
MM912F634
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