MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 188

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.28.3.3
The MMC controls the address buses and the data buses that interface the S12S masters (CPU, BDM) with the rest of the system
(master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal resources are connected
to specific target buses (see
4.28.3.3.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when
prioritizing accesses from different masters to the same target bus:
4.28.3.4
The MMC does not generate any interrupts
Freescale Semiconductor
•
•
CPU always has priority over BDM.
BDM has priority over CPU when its access is stalled for more than 128 cycles. In the later case the CPU will be stalled
after finishing the current operation and the BDM will gain access to the bus.
Chip Bus Control
Interrupts
Master Bus Prioritization Regarding Access Conflicts on Target Buses
DBG
Figure
56).
FLASH
Figure 56. S12S Platform
MMC “Crossbar Switch”
resources
CPU
BDM
XBUS0
S12X0
SRAM
Memory Mapping Control (S12SMMCV1)
S12X1
Peripherals
BDM
IPBI
MM912F634
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