MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 296

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
The ACCERR flag will also be set if the MCU enters stop mode while any command is active (CCIF=0). The
operation is aborted immediately and, if burst programming, any pending burst program command is purged (see
Section 4.36.5.2, “Stop
The ACCERR flag will not be set if any Flash register is read during a valid command write sequence.
If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return invalid data and the
ACCERR flag will not be set.
If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write
sequence (see
4.36.4.3.2
The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence, if
any of the following illegal operations are attempted, causing the command write sequence to immediately abort:
If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence
(see
4.36.5
4.36.5.1
If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be
completed.
The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see
“Interrupts"”).
4.36.5.2
If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program
or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If
active, the high voltage circuitry to the Flash array will immediately be switched off when entering stop mode. Upon exit from stop
mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting
a command write sequence (see
Freescale Semiconductor
9.
1.
2.
3.
4.
Section 4.36.3.4, “Flash Status Register
Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence.
Writing the program command if the address written in the command write sequence was in a protected area of the
Flash array.
Writing the sector erase command if the address written in the command write sequence was in a protected area of the
Flash array.
Writing the mass erase command while any Flash protection is enabled.
Writing an invalid command if the address written in the command write sequence was in a protected area of the Flash
array.
Operating Modes
Section 4.36.3.4, “Flash Status Register
Wait Mode
Stop Mode
Flash Protection Violations
As active commands are immediately aborted when the MCU enters stop mode, it is strongly
recommended that the user does not use the STOP instruction during program or erase
operations.
Mode"”).
Section 4.36.4.1.2, “Command Write
(FSTAT)"”).
(FSTAT)"”).
NOTE
Sequence"”).
32 kbyte Flash Module (S12SFTSR32KV1)
Section 4.36.8,
MM912F634
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