MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 218

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
Table 261. DBGC1 Field Descriptions (continued)
4.31.3.2.2
Table 263. Debug Status Register (DBGSR)
Read: Anytime
Write: Never
Table 264. DBGSR Field Descriptions
Freescale Semiconductor
Address: 0x0021
Reset
POR
DBGBRK
COMRV
W
R
Field
TRIG
Field
BDM
TBF
1–0
6
4
3
7
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of comparator status.
When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit
always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If
tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined by
the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing
session.
0 Do not trigger until the state sequencer enters the Final State.
1 Enter Final State immediately and issue forced breakpoint request on tracing completion
Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter Background Debug
Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM
module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12SDBGV1 Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching
0 No Breakpoint generated
1 Breakpoint generated
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window
of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore, these bits determine which register
is visible at the address 0x0027. See
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If
this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in
DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no
affect on this bit.
This bit is also visible at DBGCNT[7].
TBF
—
0
7
the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If
tracing is not enabled, the breakpoint is generated immediately.
Table 262. COMRV Encoding
Debug Status Register (DBGSR)
COMRV
00
01
10
11
0
0
0
6
Visible Comparator
Comparator A
Comparator B
Comparator C
5
0
0
0
None
Table
262.
0
0
0
4
Description
Description
Visible Register at 0x0027
0
0
0
3
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
S12S Debug (S12SDBGV1) Module
0
0
2
SSF1
1
0
0
MM912F634
SSF0
0
0
0
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