MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 123

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 140. Lx Status Register (LXR)
Table 142. Lx Control Register (LXCR)
Note:
Note:
Functional Description and Application Information
4.16
Six High Voltage capable inputs are implemented with the following features:
When used as analog inputs to sense voltages outside the module a series resistor must be used on the used input. When a Lx
input is not selected in the analog multiplexer, the voltage divider is disconnected from that input. When a Lx input is selected in
the analog multiplexer, it will be disconnected in low power mode if configured as Wake-up input. Unused Lx pins are
recommended to be connected to GND to improve EMC behavior.
4.16.1
4.16.1.1
Offset
106.
4.16.1.2
Offset
107.
Freescale Semiconductor
Table 141. LXR - Register Field Descriptions
Table 143. LXCR - Register Field Descriptions
Reset
W
W
R
R
•
•
•
L[5-0]DS
(106)
(107)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
L[5-0]
Field
Field
5-0
Digital Input Capable
Analog Input Capable with selectable voltage divider.
Wake-up Capable during Low Power mode. See
0x08
0x09
High Voltage Inputs - Lx
Register Definition
Lx Status Register (LXR)
Lx Control Register (LXCR)
7
0
7
0
0
Lx Status Register - Current Digital State of the Lx Input
Analog Input Divider Ratio Selection - Lx
0 - 2 (typ.)
1 - 7.2 (typ)
6
0
6
0
0
L5DS
L5
0
5
5
Section 4.8, “Wake-up / Cyclic
L4DS
L4
0
4
4
Description
Description
L3DS
L3
0
3
3
L2DS
Sense".
L2
0
2
2
High Voltage Inputs - Lx
L1DS
L1
1
1
0
Access: User read/write
Access: User read
MM912F634
L0DS
L0
0
0
0
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